The present invention relates to a timer control circuit for controlling an output of a timer incorporated in a computer such as a microcomputer. More particularly, the present invention relates to a timer control circuit capable of providing a complicated output waveform without casting a burden upon software.
Conventionally, there is known the circuit shown in FIG. 5 that outputs signals having various waveforms from an external output terminal of a microcomputer by using an output signal of a timer incorporated in the microcomputer.
This circuit includes timers T1, T2, and T3, flip-flops (xe2x80x9cF/Fxe2x80x9d) F1, F2, and F3, and switches S1 to S6. The generated signal is output from the F/Fs F1, F2, and F3. The timers T1, T2, and T3 are set in a mode to automatically down count for two periods. Initial count values in the first and second periods are set to different values.
In the circuit shown in FIG. 5, the F/Fs are toggled based on an underflow signal or an overflow signal output from the respective timers T1, T2, and T3 when counting corresponding to one period is finished.
For example, When the timer T1 is started, it begins counting as shown in FIG. 6. If the switch S1 is ON at two time points t1 and t2 when the timer T1 has output an underflow signal, then an output signal of the flip-flop F1 is inverted and an output signal that is a one shot pulse can be generated.
Furthermore, a complicated waveform including two pulses maybe output by using any of the following two methods.
Method 1: This is a method used when one timer is provided for one flip-flop. For example, as shown in FIG. 5, only one timer T1 is connected to the flip-flop F1. When the timer T1 is started it begins counting as shown in FIG. 7. If the switch S1 is ON at two time points t1 and t2 when the timer T1 has output an underflow signal, then an output signal of the flip-flop F1 is inverted and an output signal of one shot pulse can be generated. Thereafter, the count value of the timer T1 is re-set, and the timer T1 is started again. As a result, the output signal of the flip-flop F1 is inverted at two time points t3 and t4 when the timer T1 has output an underflow signal, and a second pulse having a different width can be output.
Method 2: This is a method used when two or more timers are provided with one flip-flop. For example, as shown in FIG. 5, three timers T1, T2, and T3 are connected to the flip-flop F2. When the timers T1 and T2 are simultaneously started, the switch S2 is set ON. As shown in FIG. 8, the timers T1 and T2 begin counting. At a time point t1, the timer T1 outputs a first underflow signal, and an output of the flip-flop F2 is inverted. Subsequently, the switch S3 is changed to the ON state. If thereafter two underflow signals have been output from the timer T2, then the switch S2 is changed to the ON state. As a result, the output of the flip-flop F2 is inverted at a time point t2 when a first underflow signal has been output from the timer T2. Furthermore, at a time point t3 when a second underflow signal has been output from the timer T2, the output of the flip-flop F2 is inverted. Thereafter, the timer T1 causes a second underflow, and the output of the flip-flop F2 is inverted at a time point t4. As a result, the two-pulse waveform as shown in FIG. 4 is generated. Thus, in this technique, an output waveform as shown in FIG. 8 is obtained by selecting one among a plurality of timers by using switches.
Thus, in the conventional timer control circuit, one timer is started a plurality of times or one of a plurality of timers is selected when generating a complicated output waveform including two or more pulses. Therefore, switching of the states of the switches S1 to S6 and counter re-setting need to be conducted by software in a personal computer. This is disadvantageous because it increases the load of the software.
It is an object of this invention to provide a timer control circuit capable of simply providing a desired out put waveform without burdening the software with a load even in the case of a complicated waveform.
The timer control circuit of one aspect of this invention comprises a plurality of timers. Each timer counts up to a predetermined value and outputs an underflow signal when counting is over. Furthermore, a logic unit receives a control signal and the underflow signals from all of the timers, and based on the control signal passes one of the underflow signals as a toggle signal. Furthermore, a control unit receives the toggle signal from the logic unit. The control unit changes its output state based on the input timing of the toggle signal.
The timer control circuit of another aspect of this invention comprises a plurality of timers. Each timer counts up to a predetermined value, generates and outputs an enable during counting, and outputs an underflow signal when counting is over. Furthermore, a plurality of logic units commonly receive an underflow signal output from one of the timers and an enable signal output from at least one of the timers. Each logic unit receives a control signal and the underflow signals from some of the timers and based on the control signal passes one of the underflow signals as a toggle signal only during an effective interval of the enable signal(s). Furthermore, there are provided a plurality of control units. Each control unit receives the toggle signal from corresponding one of the logic units. Each control unit changes its output state based on the input timing of the toggle signal.
The timer control circuit of still another aspect of this invention comprises a plurality of timers. Each timer counts up to a predetermined value and outputs an overflow signal when counting is over. Furthermore, a logic unit receives a control signal and the overflow signals from all of the timers, and based on the control signal passes one of the overflow signals as a toggle signal. Furthermore, a control unit receives the toggle signal from the logic unit. The control unit changes its output state based on the input timing of the toggle signal.
The timer control circuit of still another aspect of this invention comprises a plurality of timers. Each timer counts up to a predetermined value, generates and outputs an enable during counting, and outputs an overflow signal when counting is over. Furthermore, a plurality of logic units commonly receive an overflow signal output from one of the timers and an enable signal output from at least one of the timers. Each logic unit receives a control signal and the overflow signals from some of the timers and based on the control signal passes one of the overflow signals as a toggle signal only during an effective interval of the enable signal(s). Furthermore, a plurality of control units are provided. Each control unit receives the toggle signal from corresponding one of the logic units. Each control unit changes its output state based on the input timing of the toggle signal.